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High-level estimation and exploration of reliability for multi-processor system-on-chip
- 作者： Wang, Zheng, author.
- 其他作者：
- 其他題名：
- Computer architecture and design methodologies.
- 出版： Singapore : Springer Singapore :Imprint: Springer
- 叢書名： Computer architecture and design methodologies,
- 主題： Systems on a chip. , Fault-tolerant computing. , Engineering. , Circuits and Systems. , Performance and Reliability. , Electronic Circuits and Devices.
- ISBN： 9789811010736 (electronic bk.) 、 9789811010729 (paper)
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FIND@SFXID:
CGU
- 資料類型: 電子書
- 內容註: Introduction -- Background -- Related Work -- High-level Fault Injection and Simulation -- Architectural Reliability Estimation -- Architectural Reliability Exploration -- System-level Reliability Exploration -- Conclusion and Outlook.
- 摘要註: This book introduces a novel framework for accurately modeling the errors in nanoscale CMOS technology and developing a smooth tool flow at high-level design abstractions to estimate and mitigate the effects of errors. The book presents novel techniques for high-level fault simulation and reliability estimation as well as architecture-level and system-level fault tolerant designs. It also presents a survey of state-of-the-art problems and solutions, offering insights into reliability issues in digital design and their cross-layer countermeasures.
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讀者標籤：
- 系統號： 005419024 | 機讀編目格式
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