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Design automation for timing-driven layout synthesis
- 作者: Sapatnekar, Sachin S., 1967-
- 其他作者:
- 出版: Boston : Kluwer Academic Publishers
- 叢書名: VLSI, computer architecture and digital signal processing ;SECS198
- 主題: Metal oxide semiconductors, Complementary--design and construction--Data processing , Integrated circuits--Very large scale integration--Design and construction--Data processing , Computer-aided design
- ISBN: 0792392817 :: US$116.5
- 資料類型: 圖書
- 內容註: Includes bibliographical references (p. 247-266) and index
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讀者標籤:
- 系統號: 005216222 | 機讀編目格式