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VLSI test principles and architectures design for testability / [electronic resource] :
- 其他作者：
- 出版： Amsterdam ;Boston : Elsevier Morgan Kaufmann Publishers
- 叢書名： The Morgan Kaufmann series in systems on silicon
- 主題： Integrated circuits--Very large scale integration--Testing , Integrated circuits--Very large scale integration--Design , Circuits integres a tres grande echelle--Essais. , Circuits integres a tres grande echelle--Conception et construction. , Electronic books.
- ISBN： 9780123705976 (paper) 、 0123705975 (paper)
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FIND@SFXID:
CGU
- 資料類型: 電子書
- 內容註: Includes bibliographical references and index. Chapter 1 Introduction -- Chapter 2 Design for Testability -- Chapter 3 Logic and Fault Simulation -- Chapter 4 Test Generation -- Chapter 5 Logic Built-In Self-Test -- Chapter 6 Test Compression -- Chapter 7 Logic Diagnosis -- Chapter 8 Memory Testing and Built-In Self-Test -- Chapter 9 Memory Diagnosis and Built-In Self-Repair -- Chapter 10 Boundary Scan and Core-Based Testing -- Chapter 11 Analog and Mixed-Signal Testing -- Chapter 12 Test Technology Trends in the Nanometer Age.
- 摘要註: This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume. Most up-to-date coverage of design for testability. Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures. Lecture slides and exercise solutions for all chapters are now available. Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.
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讀者標籤：
- 系統號： 005010527 | 機讀編目格式
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