Arbitrary modeling of TSVs for 3D integrated circuits [electronic resource]

• 作者： Salah, Khaled.
• 其他作者：
  • Ismail, Yehea.
  • El-Rouby, Alaa.
  • SpringerLink (Online service)
• 其他題名：
  • Analog circuits and signal processing
• 出版： Cham : Springer International Publishing :Imprint: Springer
• 叢書名： Analog circuits and signal processing
• 主題： Three-dimensional integrated circuits--Mathematical models. , Engineering , Circuits and Systems. , Electronics and Microelectronics, Instrumentation. , Processor Architectures.
• ISBN： 9783319076119 (electronic bk.) 、 9783319076102 (paper)
• FIND@SFXID: CGU
• 資料類型: 電子書
• 內容註: Introduction: Work around Moore's Law -- 3D/TSV Enabling Technologies -- TSV Modeling and Analysis -- TSV Verification -- TSV Macro-Modeling Framework -- TSV Design Applications: TSV-Based On-Chip Spiral Inductor, TSV-Based On-Chip Wireless Communications and TSV-Based Bandpass Filter -- Imperfection in TSV Modeling -- New Trends in TSV -- TSV Fabrication -- Conclusions.
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• 摘要註: This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance, and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis, and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor, and inductive-based communication system, and bandpass filtering. Introduces a robust model that captures accurately all the loss modes of a TSV, coupling parasitics between TSVs and the TSV nonlinear capacitance and resistance of the depletion region; Enables readers to use a model which is technology dependent and can be used for any TSV configuration; Reveals a novel on-chip wireless communication technique, based on TSV spiral inductors; Equips readers for fast parasitic extraction of TSVs for 3D IC design.
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